1. Field of the Invention
The present invention relates to a semiconductor apparatus and a manufacturing method thereof, in particular to a high-performance, low-cost bipolar transistor for use in a BiMOS or BiCMOS circuit, and a manufacturing method thereof.
2. Description of the Related Art
In recent years, as the integration and functionality of the semiconductor integrated circuit becomes higher, it has become very important to achieve a high-performance analog-digital mixed integrated circuit on which an analog signal processing circuit and a digital signal processing circuit are integrated. A typical method for designing a digital circuit is to use a CMOS (Complementary Metal Oxide Semiconductor) including a MOS transistor to achieve both a large size and a low electricity consumption. Accordingly, the cases where a MOS transistor is used in an analog circuit as well have increased.
The MOS transistor, however, has a defect that the transconductance (hereinafter referred to as “gm”) is low compared with the bipolar transistor. For this reason, compared with the bipolar transistor, the gain of analog circuit (signal amplification factor) is decreased, and the circuit current increases when it obtains the same gain as the bipolar transistor. Also, in the case of the MOS transistor, the current that flows between the source and drain flows the surface of the semiconductor substrate. This makes the current susceptible to the effect of the crystal lattice defect that exists on the surface of the semiconductor substrate, flicker-noise characteristic (also referred to as “1/f noise characteristic”) is deteriorated compared with the bipolar transistor.
Furthermore, the MOS transistor is inferior than the bipolar transistor in the mismatch characteristic (difference between threshold voltages of the pair transistor) which is an important factor in the analog circuit. In the case of a MOS transistor, the difference between threshold voltages of the pair transistor (hereinafter referred to as ΔVth) is affected by many factors such as variation in the size of MOS electrode, variation in thickness of gate insulation film, variation in well surface density, and variation in density of impurities in the gate Poly-Si electrode. On the other hand, in the case of a bipolar transistor, the difference between threshold voltages of the pair transistor (hereinafter referred to as ΔVbe) is determined by the two factors: variation in emitter-base junction area; and variation in density of impurities in the emitter and the base. Accordingly, ΔVbe is smaller than ΔVth.
It is understood from the above that use of a bipolar transistor in the analog circuit provides an advantageous effect to achieve the high-performance (low electricity consumption, low noise, low variation) analog circuit in the analog-digital mixed integrated circuit. However, when a bipolar transistor is loaded in the CMOS process used in the digital circuit, the following problems arise: high cost due to increase in the number of process steps; deterioration in the characteristic of the MOS transistor due to addition of thermal process or processing process for forming the bipolar transistor; and high cost due to increase in chip area (this problem arises because the bipolar transistor is larger in area than the MOS transistor).
Patent Literature 1 identified under proposes a manufacturing method of a semiconductor apparatus that can form the emitter and the base only by adding the ion implantation step and the thermal processing step into the CMOS process. According to this manufacturing method, it is possible to restrict the increase in the number of steps and addition of manufacturing processes when the manufacturing process of the bipolar transistor is incorporated into the CMOS process. Also, by using the polysilicon film as a mask, it is possible to improve the lithography step in accuracy and reduce the emitter area. In the following, this manufacturing method will be explained with reference to FIGS. 20A through 20D.
FIGS. 20A through 20D are cross-sectional views showing manufacturing steps of a bipolar transistor. As shown in FIG. 20A, an n-type buried layer 3 and an n-type epitaxial layer 2 are formed on a p-type semiconductor substrate 1, a p-type device separation area 4 is formed by the thermal diffusion of boron (B), an insulation layer 6 is formed on the surface of the epitaxial layer 2 by the selective oxidization (LOCOS) method, an oxidization layer 7 is formed on a portion of the surface of the epitaxial layer 2 in which the insulation layer 6 does not exist, and an inner base 8 is formed.
Next, as shown in FIG. 20B, a ring-like polysilicon layer 9 is formed by deposition of a polysilicon layer and etching, and an outer base area 10 is formed by performing an ion implantation of boron by using a resist layer 11 and the ring-like polysilicon layer 9 as a mask.
Subsequently, as shown in FIG. 20C, an emitter 12 and a collector contact 13 are formed by performing an ion implantation of arsenic (As) by using a resist layer 14 and the ring-like polysilicon layer 9 as a mask. Subsequently, as shown in FIG. 20D, after the resist layer 14 is removed, an insulation film 15 is deposited on the surface by the CVD (Chemical Vapor Deposition) method, then contact holes are formed at positions corresponding to the emitter 12, the collector contact 13, and the outer base area 10, and then electrodes 16 are formed with an electrode material such as aluminum (Al).
According to this manufacturing method of the bipolar transistor, the emitter contact is formed so as to be in contact with both the emitter 12 and the ring-like polysilicon layer 9. With this structure, there is no need for the emitter 12 to be larger in area than the emitter contact, which makes it possible to form a very small emitter. As a result, it is possible to reduce area of the cells and increase the number of devices formed in the semiconductor substrate. Also, with the reduction in area of emitters, the junction capacitance decreases, and the high-frequency characteristics are improved.